FIG. 1A is a schematic circuit diagram illustrating a conventional voltage regulator. FIG. 1B is a schematic timing waveform diagram illustrating associated signals processed by the conventional voltage regulator of FIG. 1A. The conventional voltage regulator 100 is a low dropout voltage regulator (also referred as a LDO voltage regulator). The voltage regulator 100 comprises a reference voltage source, a transistor MP, an operational amplifier OP, a first resistor R1 and a second resistor R2.
The operational amplifier OP is controlled according to an enabling signal EN. A negative input terminal of the operational amplifier OP receives a reference voltage Vref from the reference voltage source. A positive input terminal of the operational amplifier OP receives a feedback voltage Vfb. An output terminal of the operational amplifier OP generates an error signal Ve. The gate terminal of the transistor MP is connected to the output terminal of the operational amplifier OP. The source terminal of the transistor MP is connected to a power supply voltage Vcc. The drain terminal of the transistor MP is connected to an output terminal O of the voltage regulator 100. Moreover, a first terminal of the first resistor R1 is connected to the drain terminal of the transistor MP, and a second terminal of the first resistor R1 is connected to a node “a”. A first terminal of the second resistor R2 is connected to the node “a”, and a second terminal of the second resistor R2 is connected to a ground voltage GND. Moreover, the feedback voltage Vfb is outputted from the node “a”, and the node “a” is connected to the positive input terminal of the operational amplifier OP.
The output terminal O of the voltage regulator 100 is connected to a bulk capacitor Cb and a load 110. While the voltage regulator 100 is normally operated, the transistor MP is controlled to generate an output voltage Vout according to the error signal Ve. Moreover, the output voltage Vout from the voltage regulator 100 is stabilized by the bulk capacitor Cb. Consequently, the output terminal O of the voltage regulator 100 generates an output current Io to the load 110. Under this circumstance, the output voltage Vout may be expressed by the following formula: Vout=(1+R1/R2)×Vref.
However, since the capacitance value of the bulk capacitor Cb is very large, the magnitude of the output current Io from the output terminal O of the voltage regulator 100 is very large during the transient period of starting up the voltage regulator 100. Consequently, the load 110 or the transistor MP is possibly burnt out. Hereinafter, the relationships between the output voltage Vout and the output current Io of the voltage regulator 100 in some situations will be described in more details.
Please refer to FIG. 1B. At the time point t1, the voltage regulator 100 is started. The high level state of the enabling signal EN indicates that the operational amplifier OP is in a normal working state. Consequently, the power supply voltage Vcc increases at a ramp rate. Obviously, during the period of increasing the power supply voltage Vcc, an overshoot phenomenon 120 of the output voltage Vout occurs and the output current Io is unstable.
At the time point t2, the power supply voltage Vcc is in the steady state (e.g. 3.3V), and the enabling signal EN is switched from a low level state to the high level state. Obviously, during the transient period of enabling the operational amplifier OP, an overshoot phenomenon 122 of the output voltage Vout occurs and the output current Io is a rush current. The rush current is larger than 2 A (2000 mA). Consequently, the load 110 or the transistor MP is possibly burnt out by the output current Io.
At the time point t3, the enabling signal EN is in the high level state. Consequently, the power supply voltage Vcc quickly increases from 0V to 3.3V. Obviously, during the transient period of starting up the voltage regulator 100, an overshoot phenomenon 124 of the output voltage Vout occurs and the output current Io is a rush current. The rush current is larger than 0.5 A (500 mA). Consequently, the load 110 or the transistor MP is possibly burnt out by the output current Io.
Generally, during the transient period of starting up the voltage regulator 100, the voltage difference between the two input terminals of the operational amplifier OP is very large. Consequently, the magnitude of the output current Io from the transistor MP is too large and the output voltage Vout has the overshoot phenomenon.
For avoiding the generation of the rush current during the transient period of starting up the voltage regulator 100, some soft-start circuits have been disclosed in for example U.S. Pat. No. 8,704,506, U.S. Pat. No. 7,459,891, U.S. Pat. No. 7,619,397 and U.S. Pat. No. 6,969,977. The soft-start circuit is applied to the voltage regulator to reduce the possibility of generating the rush current during the transient period of starting up the voltage regulator.